This invention relates to methods of manufacture of semiconductor devices, and more particularly to methods of manufacture of features of semiconductor devices by a sequence of steps including hard mask forming techniques.
Contemporary integrated circuit products require a large number of on-chip memory devices. On a typical microprocessor chip, more than two-thirds (⅔) of the surface area of the chip is occupied by Static Random Access Memory (SRAM) devices.
As integrated circuit dimensions inexorably become smaller and smaller thereby reducing the size of FET devices, we have found that it becomes more and more difficult to continue the trend of scaling SRAM devices to smaller sizes, mainly due to limitations of photolithographic resolution.
Using spacers to pattern sublithographic single features having constant widths has been proposed for FinFET patterning. A prior art approach to forming RSD regions in FinFET devices which illustrates the problems described above is shown in a paper by Yang-Kyu Choi, Tsu-Jae King, and Chenming Hu entitled “A Spacer Patterning Technology for Nanoscale CMOS” IEEE Transactions on Electron Devices, Vol. 49, No. 3, March 2002, PP. 436-441 describes a spacer patterning technology using a sacrificial layer and CVD spacer layer wherein the minimum sized features are finished not by photolithography but the CVD film thickness A set of FinFET devices is formed a Silicon-On-Insulator (SOI) substrate formed of a Buried Oxide (BOX) substrate covered with a thin insulator layer covered in turn by a polysilicon layer covered in turn by a silicon oxide hard mask layer. Two parallel, rectangular sacrificial SiGe features with vertical sidewalls are formed on the surface of the hard mask layer. Next, the sidewalls of the SiGe features are lined with Phospho-Silicate Glass (PSG) sidewall spacers, which also have vertical sidewalls. Then the sacrificial SiGe features are removed by selective dry etching leaving PSG spacer structures. Residues of SiGe were then removed by a selective wet etch. Then two source drains masks were then formed across the distal ends of the PSG spacer structures. Next, source/drain regions and fins of a FinFET device are formed by dry etching away the hard mask in a CF4 atmosphere and the polysilicon unprotected by the masks and the PSG features by etching in Cl2 and HBr gas atmosphere. However, the FinFET application described by Choi et al. is very limited because the width of the patterned feature can not be adjusted.
In an SRAM device, it is required that the pull down NFET must be stronger than the pass-gate NFET in order for SRAM to be stable, i.e., not to be disturbed during the read process. This requires width of the pull down NFET must be greater than the width of the pass gate.
U.S. Pat. No. 6,709,982 of Buynoski et al. entitled “Double spacer FinFET Formation” describes a method for forming a group of structures in a semiconductor device. Start by forming a conductive layer on a substrate, where the conductive layer includes a conductive material. Then form an oxide layer over the conductive layer. Then etch at least one opening in the oxide layer, fill at least one opening with the conductive material, etch the conductive material to form spacers along sidewalls of that one opening, and remove the oxide layer and a portion of the conductive layer to form the group of structures.
U.S. Pat. No. 5,023,203 of Choi entitled “Method of Patterning Fine Line Width Semiconductor Topology Using a Spacer” describes a method for reducing the line widths produced by patterning a semiconductor substrate with a multilayer resist mask employing a spacer-forming oxide layer over the mask after an aperture for exposing a lower resist layer has been formed in an upper portion of the multilayer mask, but prior to etching a lower resist layer. The oxide layer is subjected to a dry systemic etch to vertically remove material of the oxide layer down to the surface of the lower resist layer. Because of the substantial step coverage of the oxide layer, a spacer or stringer portion remains along the sidewalls of the original aperture in the upper portion of the mask, whereby the dimensions of the exposure window are reduced. Retaining this sidewall spacer as an integral part of mask structure permits narrower line widths to be replicated in the underlying substrate.